page 1 of 10 the SP4304 is a 75-ohm high-linearity, 6-bit rf digital step attenuator (dsa) covering a 31.5 db attenuation range in 0.5 db steps. the SP4304 provides both a parallel (latched or direct mode) and serial cmos control interface, operates on a single 3-volt supply and maintains high attenuation accuracy over frequency and temperature. it also has a unique control interface that allows the user to select an initial attenuation state at power-up. the SP4304 exhibits very low insertion loss and low power consumption. this functionality is delivered in a 4x4 mm qfn footprint. the SP4304 is manufactured on sipat?s cmos process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. product specification 75 ? rf digital attenuator 6-bit, 31.5 db, dc ? 2.0 ghz product description figure 1. functional schematic diagram SP4304 features ? 75 ? impedance ? attenuation: 0.5 db steps to 31.5 db ? low distortion for catv and multi-carrier applications ? flexible parallel and serial programming interfaces ? unique power-up state selection ? positive cmos control logic ? high attenuation accuracy and linearity over temperature and frequency ? very low power consumption ? single-supply operation ? packaged in a 20 lead 4x4 mm qfn table 1. electrical specifications @ +25 c, v dd = 3.0 v, z o = 75 ? notes: 1. device linearity will begin to degrade below 1mhz 2. max input rating in table 3 & figures on pages 4 to 6 for data across frequency. 3. note absolute maximum in table 3. 4. measured in a 50 ? system. control logic interface parallel control power-up control serial control rf input rf output switched attenuator array 6 3 2 parameter test conditions frequency minimum typical maximum units operation frequency dc 2000 mhz insertion loss 2 dc 1.2 ghz - 1.4 1.8 db attenuation accuracy any bit or bit combination dc 1.2 ghz - - (0.15 + 4% of attenuation setting) db 1 db compression 3,4 1 mhz 1.2 ghz 30 34 - dbm input ip3 1,2,4 two-tone inputs up to +18 dbm 1 mhz 1.2 ghz - 52 - dbm return loss dc 1.2 ghz 10 13 - db switching speed 50% control to 0.5 db of final value - - 1 s figure 2. package type 4x4 mm 20-lead qfn t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4304 page 2 of 10 table 2. pin descriptions electrostatic discharge (esd) precautions when handling this cmos device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rate specified in table 3. exposed solder pad connection the exposed solder pad on the bottom of the package must be grounded for proper device operation. note 1: both rf ports must be dc blocked with an external series capacitor or held at 0 v dc . 2: latch enable (le) has an internal 100 k ? resistor to v dd. 3: connect pin 12 to gnd to enable internal negative voltage generator. connect pin 12 to v ss (-v dd ) to bypass and disable internal negative voltage generator. 4. place a 10 k ? resistor in series, as close to pin as possible. figure 3. pin configuration (top view) latch-up avoidance unlike conventional cmos devices, cmos devices are immune to latch-up. switching frequency the SP4304 has a maximum 25 khz switching rate. resistor on pin 1 & 3 a 10 k ? resistor on the inputs to pin 1 & 3 (see figure 5) will eliminate package resonance between the rf input pin and the two digital inputs. specified attenuation error versus frequency performance is dependent upon this condition. v dd pup1 pup2 v dd gnd 1 20 19 18 17 16 15 14 13 12 11 6 7 8 9 10 2 3 4 5 c16 rf1 data clock le gnd vss/gnd p/s rf2 c8 c4 c2 gnd c1 c0.5 20-lead qfn 4x4mm exposed solder pad pin no. pin name description 1 c16 attenuation control bit, 16db (note 4). 2 rf1 rf port (note 1). 3 data serial interface data input (note 4). 4 clock serial interface clock input. 5 le latch enable input (note 2). 6 v dd power supply pin. 7 pup1 power-up selection bit, msb. 8 pup2 power-up selection bit, lsb. 9 v dd power supply pin. 10 gnd ground connection. 11 gnd ground connection. 12 v ss /gnd negative supply voltage or gnd connection(note 3) 13 p/s parallel/serial mode select. 14 rf2 rf port (note 1). 15 c8 attenuation control bit, 8 db. 16 c4 attenuation control bit, 4 db. 17 c2 attenuation control bit, 2 db. 18 gnd ground connection. 19 c1 attenuation control bit, 1 db. 20 c0.5 attenuation control bit, 0.5 db. paddle gnd ground for proper operation table 3. absolute maximum ratings table 4. operating ranges symbol parameter/conditions min max units v dd power supply voltage -0.3 4.0 v v i voltage on any input -0.3 v dd + 0.3 v t st storage temperature range -65 150 c p in input power (50 ? ) +30 dbm v esd esd voltage (human body model) 500 v parameter min typ max units v dd power supply voltage 2.7 3.0 3.3 v i dd power supply current 100 a digital input high 0.7xv dd v digital input low 0.3xv dd v digital input leakage 1 a input power +24 dbm temperature range -40 85 c t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4304 page 3 of 10 evaluation kit the digital attenuator evaluation kit board was designed to ease customer evaluation of the SP4304 digital step attenuator. j9 is used in conjunction with the supplied dc cable to supply v dd , gnd, and ?v dd . if use of the internal negative voltage generator is desired, then do not connect ?v dd (black banana plug). if an external ? v dd is desired, then apply -3v. j1 should be connected to the parallel port of a pc with the supplied ribbon cable. the evaluation software is written to operate the dsa in serial mode, so switch 7 (p/s) should be on with all other switches off. using the software, enable or disable each attenuation setting to the desired combined attenuation. the software automatically programs the dsa each time an attenuation state is enabled or disabled. to evaluate the power up options, first disconnect the parallel ribbon cable from the evaluation board. the parallel cable must be removed to prevent the pc parallel port from biasing the control pins to unknown states. during power up in serial mode (p/ s=1 and le=0) or in parallel mode with p/s=0 and le=1, the default power-up signal attenuation is set to the value present on the six control bits on the six parallel data inputs (c0.5 to c16). this allows any one of the 64 attenuation settings to be specified as the power-up state. to power up in parallel mode (p/s=0) with le=0, the control bits are automatically set to one of four possible values. these four values are selected by the two power-up control bits, pup1 and pup2, as shown in the parallel pup truth table (table 6). figure 4. evaluation board layout figure 5. evaluation board schematic note: resistors on pins 1 and 3 are required to avoid package resonance and meet error specifications over frequency. t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4304 page 4 of 10 -35 -30 -25 -20 -15 -10 -5 0 0 400 800 1200 1600 2000 return loss (db) rf frequency (mhz) -40 -35 -30 -25 -20 -15 -10 -5 0 0 400 800 1200 1600 2000 input return loss (db) rf frequency (mhz) 31.5db 8db 16db 0 5 10 15 20 25 30 35 0 400 800 1200 1600 2000 attenuation (db) rf frequency (mhz) 31.5db 16db 8db 4db 2db 0.5db 1db -5 -4 -3 -2 -1 0 0 400 800 1200 1600 2000 insertion loss (db) rf frequency (mhz) typical performance data @ 25c, v dd = 3.0 v (unless otherwise specified) figure 7. attenuation at major steps figure 9. output return loss at major attenuation steps figure 8. input return loss at major attenuation steps figure 6. insertion loss t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4304 page 5 of 10 -0.6 -0.4 -0.2 0 0.2 0.4 0 5 10 15 20 25 30 35 40 error 510 mhz 10mhz error 85 500mhz, -40c 500mhz, 85c 500mhz, 25c -0.4 -0.2 0 0.2 0.4 0.6 0 5 10 15 20 25 30 35 40 attenuation error (db) attenuation setting (db) 10 mhz, -40c 10mhz, 85c 10mhz, 25c -1 -0.75 -0.5 -0.25 0 0.25 0.5 0 5 10 15 20 25 30 35 40 attenuation e rror (db) attenuation setting (db) 10mhz 1210mhz 1010mhz 750mhz 510mhz 250mhz -2 -1.5 -1 -0.5 0 0.5 1 0 400 800 1200 1600 2000 attenuation error (db) rf frequency (mhz) 8db 16db 31.5db figure 11. attenuation error vs. attenuation setting figure 13. attenuation error vs. attenuation setting figure 12. attenuation error vs. attenuation setting figure 10. attenuation error vs. frequency typical performance data @ 25c, v dd = 3.0 v (unless otherwise specified) note: positive attenuation error indicates higher attenuation than target value t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4304 page 6 of 10 20 25 30 35 40 45 50 55 60 0 400 800 1200 1600 2000 input ip3 (dbm) rf frequency (mhz) 0 5 10 15 20 25 30 35 40 0 400 800 1200 1600 2000 compression (db) rf frequency (mhz) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0 5 10 15 20 25 30 35 40 attenuation error (db) attenuation setting (db) 1200mhz, 85c 1200mhz, 25c 1200mhz, -40c -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0 5 10 15 20 25 30 35 40 attenuation error (db) attenuation setting (db) 1000mhz, -40c 1000mhz, 85c 1000mhz, 25c figure 15. input ip3 vs. frequency figure 16. input 1db compression (major attenuation states, 50 ? system) figure 14. attenuation error vs. frequency typical performance data @ 25c, v dd = 3.0 v (unless otherwise specified) figure 17. input ip3 vs. frequency (major attenuation states, 50 ? system) note: positive attenuation error indicates higher attenuation than target value t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4304 page 7 of 10 programming options parallel/serial selection either a parallel or serial interface can be used to control the SP4304. the p/s bit provides this selection, with p/s=low selecting the parallel interface and p/s=high selecting the serial interface. parallel mode interface the parallel interface consists of five cmos- compatible control lines that select the desired attenuation state, as shown in table 5. the parallel interface timing requirements are defined by figure 19 (parallel interface timing diagram), table 9 (parallel interface ac characteristics), and switching speed (table 1). for latched parallel programming the latch enable (le) should be held low while changing attenuation state control values, then pulse le high to low (per figure 19) to latch new attenuation state into device. for direct parallel programming, the latch enable (le) line should be pulled high. changing attenuation state control values will c hange device state to new attenuation. direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers). table 5. truth table note: not all 64 possible combinations of c0.5-c16 are shown in table serial interface the serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. it is controlled by three cmos-compatible signals: data, clock, and latch enable (le). the data and clock inputs allow data to be serially entered into the shift register, a process that is independent of the state of the le input. the le input controls the latch. when le is high, the latch is transparent and the contents of the serial shift register control the attenuator. when le is brought low, data in the shift register is latched. the shift register should be loaded while le is held low to prevent the attenuator value from changing as data is entered. the le input should then be toggled high and brought low again, latching the new data. the timing for this operation is defined by figure 18 (serial interface timing diagram) and table 8 (ac characteristics). power-up control settings the SP4304 always assumes a specifiable attenuation setting on power-up. this feature exists for both the serial and parallel modes of operation, and allows a known attenuation state to be established before an initial serial or parallel control word is provided. when the attenuator powers up in serial mode (p/ s=1), the six control bits are set to whatever data is present on the six parallel data inputs (c0.5 to c16). this allows any one of the 64 attenuation settings to be specified as the power-up state. when the attenuator powers up in parallel mode (p/ s=0) with le=0, the control bits are automatically set to one of four possible values. these four values are selected by the two power-up control bits, pup1 and pup2, as shown in table 6 (power-up truth table, parallel mode). table 6. parallel pup truth table note: power up with le=1 provides normal parallel operation with c0.5-c16, and pup1 and pup2 are not active. p/s c16 c8 c4 c2 c1 c0.5 attenuation state 0 0 0 0 0 0 0 reference loss 0 0 0 0 0 0 1 0.5 db 0 0 0 0 0 1 0 1 db 0 0 0 0 1 0 0 2 db 0 0 0 1 0 0 0 4 db 0 0 1 0 0 0 0 8 db 0 1 0 0 0 0 0 16 db 0 1 1 1 1 1 1 31.5 db p/s le pup2 pup1 attenuation state 0 0 0 0 reference loss 0 0 1 0 8 db 0 0 0 1 16 db 0 0 1 1 31 db 0 1 x x defined by c0.5-c16 t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4304 page 8 of 10 table 7. 6-bit attenuator serial programming register map table 9. parallel interface ac characteristics figure 19. parallel interface timing diagram table 8. serial interface ac characteristics figure 18. serial interface timing diagram le clock data msb lsb t lesup t sdsup t sdhld t lepw b5 b4 b3 b2 b1 b0 c16c8c4c2c1c0.5 lsb (last in) msb (first in) note: f clk is verified during the functional pattern test. serial programming sections of the functional pattern are clocked at 10 mhz to verify f clk specification. v dd = 3.0 v, -40 c < t a < 85 c, unless otherwise specified t pdsup t pdhld parallel data c16:c0.5 le t lepw v dd = 3.0 v, -40 c < t a < 85 c, unless otherwise specified symbol parameter min max unit f clk serial data clock frequency (note 1) 10 mhz t clkh serial clock high time 30 ns t clkl serial clock low time 30 ns t lesup le set-up time after last clock falling edge 10 ns t lepw le minimum pulse width 30 ns t sdsup serial data set-up time before clock rising edge 10 ns t sdhld serial data hold time after clock falling edge 10 ns symbol parameter min max unit t lepw le minimum pulse width 10 ns t pdsup data set-up time before rising edge of le 10 ns t pdhld data hold time after falling edge of le 10 ns t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4304 page 9 of 10 figure 20. package drawing 1.00 1.00 2.00 2.00 0.23 0.10 c a b exposed pad 4.00 detail a 16 15 11 5 1 6 20 10 0.50 typ 2.00 typ 0.55 2 1 detail a 0.18 0.18 0.435 0.435 seating plane 0.08 c 0.10 c 0.020 0.20 ref exposed pad & terminal pads 0.80 - c - 2.00 x 2.00 2.00 2.00 4.00 4.00 - b - - a - index area 0.25 c 1. dimension applies to metallized terminal and is measured between 0.25 and 0.30 from terminal tip. 2. coplanarity applies to the exposed heat sink slug as well as the terminals. 3. dimensions are in millimeters. t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
product specification SP4304 page 10 of 10 figure 21. marking specifications figure 22. tape and reel drawing 4304 yyww zzzzz yyww = date code zzzzz = last five digits of psc lot number t e l : +86-23 - 628 0 8 8 18 f ax: +86-23-6 2 80 5 284 ww w . s i patsa w . com / sawmkt@s i p at.com
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